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Mojo struct
RaggedMHAOperand
struct RaggedMHAOperand[origin: ImmOrigin, cache_origin: ImmOrigin, //, dtype_: DType, layout: TensorLayout, cache_layout: TensorLayout, scale_dtype_: DType = dtype_, scale_layout: TensorLayout = Layout[*?, *?]]
An implementation for ragged contiguous tensor arguments to MHA kernels.
Fields
- buffer (
TileTensor[RaggedMHAOperand[dtype_, layout, cache_layout, scale_dtype_, scale_layout].dtype, layout, origin]): - scale_buffer (
TileTensor[RaggedMHAOperand[dtype_, layout, cache_layout, scale_dtype_, scale_layout].scale_dtype, scale_layout, ImmutAnyOrigin]): - cache_row_offsets (
TileTensor[DType.uint32, cache_layout, cache_origin]):
Implemented traits
AnyType,
Copyable,
Deinitable,
DevicePassable,
ImplicitlyCopyable,
MHAOperand,
Movable,
RegisterPassable,
TrivialRegisterPassable
comptime members
device_type
comptime device_type = RaggedMHAOperand[dtype_, layout, cache_layout, scale_dtype_, scale_layout]
dtype
comptime dtype = dtype_
page_size
comptime page_size = 0
quantization_enabled
comptime quantization_enabled = False
quantization_granularity
comptime quantization_granularity = 0
scale_dtype
comptime scale_dtype = scale_dtype_
Methods
__init__
def __init__(buffer: TileTensor[Self.dtype, layout, origin], cache_row_offsets: TileTensor[DType.uint32, cache_layout, cache_origin]) -> Self
def __init__(buffer: TileTensor[Self.dtype, layout, origin], scale_buffer: TileTensor[Self.scale_dtype, scale_layout, ImmutAnyOrigin], cache_row_offsets: TileTensor[DType.uint32, cache_layout, cache_origin]) -> Self
get_type_name
block_paged_ptr
def block_paged_ptr[tile_size: Int](self, batch_idx: UInt32, start_tok_idx: UInt32, head_idx: UInt32, head_dim_idx: UInt32 = UInt32(0)) -> Pointer[Scalar[Self.dtype], ImmutAnyOrigin]
Returns:
Pointer[Scalar[Self.dtype], ImmutAnyOrigin]
scales_block_paged_ptr
def scales_block_paged_ptr(self, batch_idx: Int, start_tok_idx: Int, head_idx: Int, head_dim_idx: Int = Int(0)) -> Pointer[Scalar[Self.scale_dtype], ImmutAnyOrigin]
Returns:
Pointer[Scalar[Self.scale_dtype], ImmutAnyOrigin]
load_scale
def load_scale[width: Int](self, batch_idx: Int, start_tok_idx: Int, head_idx: Int, head_dim_idx: Int) -> SIMD[Self.scale_dtype, width]
Returns:
cache_length
max_context_length
num_kv_rows
row_idx
def row_idx(self, batch_idx: UInt32, start_tok_idx: UInt32) -> UInt32
Returns the row idx when viewing the memory as a matrix.
Returns:
get_tma_row
def get_tma_row(self, encoded_index: Int32) -> Int32
Convert an encoded sparse index to a physical TMA row.
Non-paged operand: identity (no paging translation needed).
Returns:
create_tma_tile
def create_tma_tile[swizzle_mode: TensorMapSwizzle, *, BN: Int, depth: Int, BK: Int = padded_depth[dtype_, swizzle_mode, depth](), fold_chunks: Int = Int(1), row_major: Bool = False](self, ctx: DeviceContext, out tma: TMATensorTile[Self.dtype, Int(3), _padded_shape[Int(3), Self.dtype, IndexList(BN, Int(1), BK, __list_literal__=NoneType(None)), swizzle_mode](), _ragged_shape[Int(3), Self.dtype, IndexList(BN, Int(1), BK, __list_literal__=NoneType(None)), swizzle_mode]()])
Creates a TMA tile for efficient GPU memory transfers.
Returns:
create_scale_tma_tile
def create_scale_tma_tile[BMN: Int](self, ctx: DeviceContext, out tma: TMATensorTile[Self.scale_dtype, Int(2), Index[Int, Int](Int(1), BMN)])
Returns:
TMATensorTile[Self.scale_dtype, Int(2), Index[Int, Int](Int(1), BMN)]
create_rope_tma_tile
def create_rope_tma_tile[swizzle_mode: TensorMapSwizzle, *, BN: Int, BK: Int, padded_depth: Int](self, ctx: DeviceContext, out tma: TMATensorTile[DType.bfloat16, Int(3), _padded_shape[Int(3), DType.bfloat16, IndexList(BN, Int(1), BK, __list_literal__=NoneType(None)), swizzle_mode](), _ragged_shape[Int(3), DType.bfloat16, IndexList(BN, Int(1), BK, __list_literal__=NoneType(None)), swizzle_mode]()])
Not supported for RaggedMHAOperand.
Returns:
create_gather4_tma_tile
def create_gather4_tma_tile[tile_width: Int, tile_stride: Int = tile_width, swizzle_mode: TensorMapSwizzle = TensorMapSwizzle.SWIZZLE_NONE, tile_height: Int = Int(4), tma_dtype: DType = RaggedMHAOperand[dtype_, layout, cache_layout, scale_dtype_, scale_layout].dtype, l2_promotion: TensorMapL2Promotion = TensorMapL2Promotion.NONE](self, ctx: DeviceContext, out tma: TMATensorTile[tma_dtype, Int(2), IndexList(tile_height, _gather4_box_width[tma_dtype, tile_width, swizzle_mode](), __list_literal__=NoneType(None)), IndexList(Int(1), _gather4_box_width[tma_dtype, tile_width, swizzle_mode](), __list_literal__=NoneType(None))])
Creates a 2D TMA gather4 descriptor for this ragged operand.
Returns:
create_rope_gather4_tma_tile
def create_rope_gather4_tma_tile[tile_width: Int, padded_depth: Int, swizzle_mode: TensorMapSwizzle = TensorMapSwizzle.SWIZZLE_NONE, tile_height: Int = Int(4), l2_promotion: TensorMapL2Promotion = TensorMapL2Promotion.NONE](self, ctx: DeviceContext, out tma: TMATensorTile[DType.bfloat16, Int(2), IndexList(tile_height, _gather4_box_width[DType.bfloat16, tile_width, swizzle_mode](), __list_literal__=NoneType(None)), IndexList(Int(1), _gather4_box_width[DType.bfloat16, tile_width, swizzle_mode](), __list_literal__=NoneType(None))])
Not supported for RaggedMHAOperand.
Returns:
scales_raw_ptr
def scales_raw_ptr(self) -> Pointer[Float32, MutAnyOrigin]
Returns a dangling pointer. Ragged operands do not support quantization.
Returns:
Pointer[Float32, MutAnyOrigin]