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Mojo struct

DistributedReduceScatterSum

struct DistributedReduceScatterSum

Registers the mo.distributed.reducescatter.sum graph op with the graph compiler.

Implemented traits​

AnyType, ImplicitlyDeletable

Methods​

execute​

static def execute[dtype: DType, rank: Int, target: StringSlice[ImmStaticOrigin], _trace_name: StringSlice[ImmStaticOrigin], axis: Int = Int(0), group_size: Int = Int(0)](outputs: _FusedOutputVariadicTensors[static_specs=outputs.static_specs], inputs: VariadicTensors[IOSpec[_, _].Input, static_specs=inputs.static_specs], signal_buffers: VariadicTensors[IOSpec[_, _].MutableInput, static_specs=signal_buffers.static_specs], dev_ctxs_input: DeviceContextArray)

Distributed reduce-scatter operation implementation for sum reduction.

Limitations: - Maximum of 8 GPUs supported (matches MAX_GPUS in comm/sync.mojo) - Tensor element count must be multiple of SIMD width - Requires identical tensor shapes within each reduce-scatter group

Parameters:

  • ​dtype (DType): Element type of the input and output tensors.
  • ​rank (Int): Tensor rank (number of dimensions) of the inputs and outputs.
  • ​target (StringSlice[ImmStaticOrigin]): Target device string for tracing.
  • ​_trace_name (StringSlice[ImmStaticOrigin]): Trace name for profiling.
  • ​axis (Int): Axis along which to scatter the reduced result (defaults to 0).
  • ​group_size (Int): Number of devices per reduce-scatter group; must be at least 1 and must evenly divide the total number of devices (defaults to 0).

Args:

  • ​outputs (_FusedOutputVariadicTensors[static_specs=outputs.static_specs]): Output tensors (one per GPU) to store scattered reduced results.
  • ​inputs (VariadicTensors[IOSpec[_, _].Input, static_specs=inputs.static_specs]): Input tensors (one per GPU) containing values to reduce.
  • ​signal_buffers (VariadicTensors[IOSpec[_, _].MutableInput, static_specs=signal_buffers.static_specs]): Preallocated synchronization buffers for cross-GPU coordination.
  • ​dev_ctxs_input (DeviceContextArray): Device contexts for participating GPUs.